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Ion-trap chip architecture optimized for the implementation of quantum error-correcting codes

Jeonghoon Lee1,2, Hyeongjun Jeon1,2, and Taehyun Kim1,2,3,4,5,6,*

  • *Contact author: taehyun@snu.ac.kr
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Phys. Rev. A 113, 032432 – Published 16 March, 2026

DOI: https://doi.org/10.1103/tk99-76gb

Abstract

We propose a scalable trapped-ion quantum-computing architecture that efficiently incorporates quantum error correction. The chip design exploits orthogonal qubit connectivity by assigning horizontal trap regions to transversal logical gates and vertical regions to nontransversal gates and syndrome extraction, thereby enabling universal gate operations with minimal ion shuttling and reduced hardware complexity. Using a dedicated software tool, we evaluate the architecture on several benchmark algorithms and scheduling policies for a two-dimensional color code of varying code distance. Our results demonstrate that increasing the code distance by two reduces the effective logical two-qubit gate error probability by approximately two orders of magnitude, reaching values as low as 10−8 with the [[31,1,7]] color code. This improvement substantially expands the range of algorithms that can be executed reliably, up to scales of a few thousand logical qubits, depending on the algorithmic structure. Overall, these findings validate the practicality and scalability of the proposed architecture and its control strategies, highlighting a viable route toward fault-tolerant, trapped-ion quantum computing.

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Phys. Rev. A 113, 032432– Published 16 March, 2026
  • Received 8 December 2025
  • Accepted 18 February 2026
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